(1) Field of the Invention
This invention relates to a semiconductor device and a method for fabricating such a semiconductor device and, more particularly, to a semiconductor device having a wafer level package (WLP) structure and a method for fabricating such a semiconductor device.
(2) Description of the Related Art
In recent years attention has been riveted on a WLP technique for performing all processes, including packaging, from a process in which a chip is formed in a wafer to a process in which the wafer is diced into individual chips in a wafer state. It is expected that the WLP technique will be used for, for example, miniaturizing semiconductor devices, improving the performance of semiconductor devices, increasing the packaging density of semiconductor devices, and increasing the efficiency of a process for manufacturing semiconductor devices.
By the way, usually resin most suitable for semiconductor devices is used for manufacturing their packages with, for example, their uses or their characteristics required taken into consideration. In addition, when resin is sealed, care must be taken according to chip form so that the performance of semiconductor devices will not be deteriorated. With a chip having what is called an air bridge wiring structure, for example, to prevent resin from entering a space between wiring portions, the method of forming a dam protrusion electrode having the shape of a frame around the wiring portions has been proposed (see Japanese Unexamined Patent Publication No. 06-252208).
Usually resin is used for fabricating a package for a semiconductor device having a WLP structure, but the following problems arise.
FIG. 50 is a schematic sectional view showing an important part of an example of a conventional semiconductor device having a WLP structure.
In FIG. 50, a semiconductor device 100 which has a WLP structure and on which a dicing process has been performed by using the WLP technique is shown.
A silicon (Si) substrate 101 is used as a semiconductor substrate in the semiconductor device 100. A predetermined transistor structure (not shown) is formed in the Si substrate 101. An interlayer dielectric film 102, such as a silicon oxide (SiO2) film, is formed on the Si substrate 101. An aluminum (Al) pad 103 is formed on the interlayer dielectric film 102. The pad 103 is electrically connected to a transistor formed in the Si substrate 101 via a wiring (not shown) or a via (not shown) formed in the interlayer dielectric film 102. A cover film 104, such as an SiO2 film, is formed on the interlayer dielectric film 102 except on part of the surface of the pad 103. A polyimide (PI) film 105 is formed so as to cover the interlayer dielectric film 102 and the cover film 104.
In the semiconductor device 100 having the WLP structure, a copper (Cu) rewiring 106 having a predetermined pattern is formed on the pad 103 which is not covered with the cover film 104 or the PI film 105 and on the PI film 105. One end of a copper post 108 which pierces through a sealed resin 107 is connected to the rewiring 106 and the other end of the copper post 108 is connected to a solder bump 109.
The Si substrate 101 directly touches the sealed resin 107 in a scribed region 110 which remains at an edge portion of the semiconductor device 100 having the above structure. There is a comparatively great difference in thermal expansivity between the Si substrate 101 and the sealed resin 107. Accordingly, a crack 112 (indicated by a dotted line in FIG. 50) may run from a portion 111 on a side of the semiconductor device 100 where the Si substrate 101 touches the sealed resin 107 because of, for example, heat generated at the time of the operation of the semiconductor device 100 or heat generated by another element or unit located near the semiconductor device 100. If the crack 112 appears, the sealed resin 107 may peel off the Si substrate 101 or the PI film 105. If the crack 112 reaches the inside of a chip, peeling may occur inside the chip. If such peeling has occurred, there is a strong possibility that the performance of the semiconductor device 100 deteriorates.
The above problem of the peeling of a sealed resin or the like may arise not only in a semiconductor device having a WLP structure but also in a semiconductor device having, for example, a conventional chip size package (CSP) structure the fabrication of which does not need the WLP technique. That is to say, the above problem may arise in semiconductor devices that have the same structure after completion.